• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.
    公开号:SU1082341A3
    申请号:SU792781854
    申请日:1979-06-22
    公开日:1984-03-23
    发明作者:Таппен Фэрчайлд Питер；Кальвин Лейнингер Джоэл
    申请人:Интернэшнл Бизнес Машинз Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    connected to the second half of the inputs of the group of control inputs of the block and with the second input of the OR element; the outputs of the AND elements of the group are connected to the corresponding outputs of the block.
    4. The device according to claim 1, characterized in that the auxiliary control unit contains two NOT elements, two NOT-AND elements, the first input of the first element NOT-AND connected to the first input of the block, the second input of which is connected to the first input of the second element NOT -And and through the first element NOT - to the second input of the first element NOT-AND, the outputs of the first and second elements NOT-AND connected through the second element NOT to
    output of the block and with the second input of the second element NOT-AND.
    5. The device according to claim 1, characterized in that the auxiliary control block contains a NOT element, two AND elements and a trigger, wherein the first input of the first element I is connected to the first input of the block and through the NOT element to the first input of the second And element, the second input of which connected to the second inputs of the block and the first element And, the output of which is connected to the input of the trigger installation, the reset input of which is connected to the output of the second element And, the output of the trigger is connected to the output of the block.
    one
    The invention relates to a control device in digital data processing systems and, in particular, can be used in microprocessors, microcontrollers, etc.
    A known data processing system in which control devices contain control registers into which control data is written, which is used during program execution to determine a course of action in specific situations l.
    Although the control registers increase the capabilities of the main control circuit, since they can be controlled by a program, they do not allow selective setting or changing the state of individual control bits, since writing information to all 32 binary bits these registers are produced simultaneously. This is a disadvantage, especially in the case of small systems with limited capabilities such as a microprocessor.
    The closest to the invention of the technical entity is a microprocessor that contains, in addition to the usual functional blocks, a memory, an operation register or a command register connected to the memory output, a decoding or control circuit connected to the output of the operation register for generating control signals for other units. given
    microprocessor 2.
    Control signals are dependent only on the present contents of the operation register and, thus, this microprocessor has
    to some extent limited control.
    The aim of the invention is to obtain greater flexibility in managing the data processing system and to selectively change independent control parameters at the expense of the contents of a single command. The goal is achieved by the fact that the control device in
    A data processing system comprising a memory block, the output of which is connected to the information input of the command register, the control output of which is connected to the input of the decoder
    commands, contains a group of auxiliary control blocks and a load control block, with the group of outputs of the command decoder connected to the group of control inputs of the block
    load control, clock input
    which is connected to the clock input of the device, the group of information inputs of the load control block is connected to the group of address outputs of the command register, the first inputs of the auxiliary control block of the group are connected to the corresponding outputs of the register command data, the second inputs of the auxiliary control blocks of the group are connected The switches, the outputs of the auxiliary control units of the group are connected to the corresponding outputs of the device. Moreover, the load control block contains a group of elements AND, the first inputs of which are connected to the corresponding inputs of the group of information inputs of the block, the second inputs of all elements AND of the group are connected to the corresponding inputs of the group of control inputs of the block, the third inputs of all elements AND of the group are connected to the clock input of the block, the outputs of the elements And groups are connected to the corresponding outputs of the block. In addition, the load control block contains an OR element and a group of AND elements, the first inputs of the AND elements of the group are connected to the corresponding inputs of the group of information inputs of the block, the second inputs of the first and second elements of the AND group are connected to the first half of the inputs of the group of control inputs of the block and with the first input of the IL element whose upstream is connected to the second inputs of the third and fourth elements of the AND group, the second inputs of the fifth and sixth elements AND of the group are connected to the second half of the inputs of the group of control inputs of the block ka and with the second input of the OR element, the outputs of the AND elements of the group are connected to the corresponding outputs of the block. In this case, the auxiliary control block contains two NOT elements two NOT-AND elements, the first input of the first element NOT-AND connected to the first input of the block, the second input of which is connected to the first input of the second element NOT-AND and through the first element NOT to the second input the first element is NOT-AND, the outputs of the first and second elements are NOT-AND connected through the second element is NOT to the output of the block and the second input of the second element is NOT-AND. The auxiliary control block contains a NOT element, two And elements and a trigger, with the first input of the first element And connected to the first input of the block and through the element NOT to the first input of the second element And, the second input of which is connected to the second inputs of the block and the first element And whose output connected to, the installation input of the trigger, the reset input of which is connected to the output of the second element, And the output of the trigger is connected to the output of the block. Fig. 1 shows a block diagram of a control unit with a first embodiment of a load control unit; Fig. 2 is a block diagram of an auxiliary control unit, the first embodiment; Fig. 3 is the same as the second variant; Fig. 4 shows an embodiment of the use of the device in a microprocessor; FIG. 3 is a time diagram of the operation shown in FIG. 4, FIG. 6 is a block diagram of a control device with a second embodiment of the load control unit. The control unit (Fig. 1) contains a memory block 1, a command register 2, a decoder for 3 commands, a load control unit 4, auxiliary control group blocks 5, a clock input 6 of the device. Block 4 (in the first embodiment) contains elements of group 7. In addition, the device contains outputs 8 and 9. Unit 5 in the first embodiment (FIG. 2) contains the elements NOT 10 and 11, elements NOT-AND 12 and 13. Block 5 in the second embodiment (FIG. 3) contains the element NOT 14, And 15 and 16 elements and trigger 17. The microprocessor (Fig. 4) contains a main memory block 18, a decoder 19, an increment block 20, a command address register 21, an And 22 element, fixing circuits 23 and 24, a main memory address register 25 , elements 26-28, register of 29 commands, decoder 30, synchronization input 31, load control block 32. The control unit with the second embodiment of the load control unit (Fig. 6) contains a memory block 33, a command register 34, a command decoder 35, a load control block 36 containing AND 37-42 group elements and an OR 43 element, auxiliary blocks 44-49 group control, clock input 50, decoders 51 and 52. The register of 2 commands receives one command from memory 1 at a time. A new command is added to write to one or more blocks 5 in the command set of the data processing device. Let's call it the Record command. To distinguish this command from other types of commands in a given set of commands, it is attached with a single pre-set opcode (OREMA). The remaining binary bits A, B, C, D, W, X, Y, Z of the Write command form the operand of this command and provide the only specific values of the address and data of the control device. In particular, bits A-D form an address field, and bits W-Z a data field. As is the case in known data processing devices, the processor in which the control device is used operates with rotating time cycles or computer cycles. Each machine cycle of a data processing unit is divided into time sequence sequences of equal duration, and for each such interval a separate clock pulse is provided. Assume that the processor CPU cycles are divided into 12 time intervals, labeled TO + T11. One of the clock pulses, for example, the pulse T 11, appearing at the input 6 at the end of the machine cycle, is fed to the third input of each element of the And 7 group of py-. Any element AND 7 of the group will trigger the write signal to the corresponding block 5 while simultaneously fulfilling three conditions, namely: the corresponding binary row of the ABCD group of the command register 2 is 1, the decoder 3 has detected the Write command () T11 is present. Thus, for example, the first element AND 7 of the group causes the write signal to the input of the corresponding block 5, when 1 is recorded in binary bit 102 (A), the output of the decoder 3 (SX) is also a single value, and a clock pulse appears at input 6 T1 1 with a logic level of 1. If, on one or more inputs of the And 7 group, the signal level is not equal to logical 1, the recording signal is not input to the input 16 of block 5. Binary bits, A, B, C, and D of the Record command define one of blocks 5 to which recording will be made upon the appearance of such a command. In bits A, B, C, and D of the corresponding blocks 5 to which recording is to be made, is logical 1. In bits A, B, C, and D of the corresponding blocks 5, which should not be written to, there is a logical O If block 5 does not receive a recording signal, its state does not change. If it is necessary to write to it, the value of the signal written to it is determined by the value recorded in the corresponding binary bit W, X, Y, and Z of the Write command. So, for example, if binary decompression W contains binary logical 1, then the write signal at the output of the group element AND 7 will write a single value to the corresponding block 5. And vice versa, if the bit contains a binary logical O, then the write signal at the output element AND 7 of the group will write the zero value into the corresponding block 5. The format of the Record command (Fig. 1) makes it possible to change the state of any one, two, three or four blocks 5 with programmed control, and the state of any such block can be changed or zero or one amenny at will. This gives considerable flexibility in setting and resetting the program-controlled blocks 5 to the initial state. Every time when the programmer needs to change the state of one or several blocks 5, he simply enters the program Write command with the corresponding values of the binary bits A, B, C, D, W, X, Y, Z. When during the execution of this program this command enters the register of 2 commands, the state of one or several blocks 5 is changed accordingly. Output values XI, X2, XS and X4 At the outputs of blocks 5, they can be used for various control purposes in the data processing system in which these blocks 5 are located. They can be used to select a memory page, directly control external devices or circuits, and for selecting various internal processor fixations. The advantage of the invention is that any of these blocks 5 can be used to perform completely different control functions in this system. For example, two such blocks 5 can be used to select a memory page, the third block 5 to control an external device, and the fourth is to control any internal function of the processor. As the state of one block 5 can be changed regardless of the state of the other blocks 5 in this system, and also whether their state changes or not, different The programs that control a particular block 5 are completely independent of the programs that control the other blocks 5. Consider two options for building a separate block (Figure 2 and 3. In the block shown in Figure 2, two HE-12 elements are used. and 13 and two elements are NOT 10 and 11. This block fixes on the output bus the same binary value that is present on the input data bus at the moment when the trailing edge of the negative input recording pulse arrives on the input write bus. If this form of construction is used for each of the blocks 5, the negative polarity recording pulses can be obtained, for example, if the element AND-AND is set instead of each AND 7 of the group. Block 5, shown in FIG. 3, contains an element NOT 14, two elements 15 and 16, and a trigger 17. In this case, a positive write pulse is used at the recording input. In the microprocessor, the processor main memory unit 18 or the main memory subsystem contains four memory locations, labeled pages. Assume that the main memory address register 25 is 12-bit, it stores 12 bits contained in the memory address field of those commands that contain the memory address field, i.e. It is assumed that this microprocessor has the ability to address the main memory of 12 bits. Thus, in this example, the instruction address register 21 (with its incrementing block 20) and the data address register are also 12-bit registers. The primary 12-bit address may address memory in the range from 0 to 4095 bytes, where each byte contains 8 bits. In this example, each page of the main memory has a capacity of 4096 bytes, and this capacity corresponds to the maximum possibility of addressing the register 25 of the address of the main memory. To achieve an incremental increase in the addressing capacity of the main memory, it is necessary to use two auxiliary control units (Fig. 1), which in Fig. 4 are designated as fixing circuits 24 and 23. The writing to the latching circuits 23 and 24 is controlled by block 32, including AND elements 26 and 27. The decoder 30 still has the ability to output the output signal SX when the Write operation code is detected in register 29 of the commands. The latching circuits 23 and 24 produce address control signals, and the microprocessor is provided with memory section selection circuits connected to the main memory subsystem 18 and responding to these address control signals, determining a specific memory location or page of memory to be accessed. These schemes for selecting a section of memory contain a decoder 19, which decodes a two-bit code from the output buses of the two fixation schemes and excites one of the four output tires of the memory picker. These page selection buses from the decoder 19 lead to different parts of the pages in the main memory 18 and select them. As only one page selection flag can be excited at any time, then only one of the four can be accessed at a time. possible memory locations. In other words, the memory address in register 25 is valid only for a specific memory page, which corresponds to the excited page selection bus. For example, if a two-digit code 00 is present at the outputs of the fixing circuit 23 24, the bus is energized. Select the first page and address from. the register (SAR) 25 is transmitted to the address chains of the first page. If code 01 is present at the outputs of circuits 23 and 24, the bus is excited. The choice of the second page and the address from the register (SAR 25 are transmitted to the address chains of the second page. Similar reasoning can be made for the third and fourth pages. If you need to use different memory pages when executing any program, simply enter the commands at the appropriate points of this program Record and the bits A, B, W and X in these commands must have the appropriate code to select on the memory window page. When using the Record command exclusively to select memory pages, this command is more correct. This would be called the selection of the memory page. The addressing ability of the main memory of the microprocessor can be further enhanced by using not three or more latching schemes (Figure 4), but three or four. The use of three latching schemes allows you to select more than eight main pages. memory, and the use of four fixation schemes allows selection of more than sixteen pages of the main memory. Thereafter, the third and fourth fixation schemes and the associated elements are included as shown in Fig. 1, with the outputs of all three and and the four fixation schemes lead to increased decoder 19, which can decrypt the three chetyrehrazr dny code and provided, respectively, 8 or 16 buses you page boron. The advantage of writing to a fixation scheme at the end of a machine cycle or near the end of this cycle, during which time a command is written to the command register, is as follows. Consider the circuit shown in Fig. 45, where the write to one or both of the latching circuits 23 and 24 is controlled by a clock pulse T11 arriving at the synchronization input 31 and the third inputs of the And 26 and 27 elements, and this clock is assumed to be T11 is the last clock pulse in the machine cycle for the Write command. The purpose that is pursued using the clock pulse that occurs at or near the end of the machine cycle to set the control signal fixation circuit is to make it possible to complete one more time. a memory cycle during which a transition command can be written to the command register 29, which will provide the transition address for the memory address register 25 before the latching circuit status changes. This makes it possible not only to change the page, but at the same time to change the address in this page, i.e. Both changes occur simultaneously with the same memory access, even if they are specified by two consecutive commands. Consider a timing diagram (Fig. 5) where the cycle is a computer cycle, during which the Write command is found in command register 29, and the N + 1 cycle represents the next cycle, during which a transition command is found in command register 29. The Write (Memory Page Selection) command is written to the command register 29 by an IR write pulse (command register) of cycle N during a TO time interval. The register contents (IAR) 21 are written to memory address register 25 by a write SAR pulse of a cycle N during T2, it is assumed that the decoder 30 provides the corresponding decode signal for driving the control logic circuit represented by AND 22. This register address (IAR) 21 is the address of the next command, which in this case is the command stroke cycle N + 1. On a memory cycle selection pulse N, an address from register (SAR) 25 is transmitted to the address circuits of the main memory 18 and soon the addressed command appears at the output of the main memory 18. Thus, the next command (which should be executed in
    cycle N + 1) is selected in advance, during the execution of the current command in cycle N.
    Only after transferring the sample to the next command to a point where it cannot be affected, can one be written to one or both of the fixation circuits 23 and 24. This is done by writing to the fixation circuit of cycle N during the interval T11, located at the very end of cycle N. Therefore, the result of a change in the state of the fixation schemes does not affect for some time until a certain later point in the next machine cycle. Thus, the transition command for the N + 1 cycle is obtained from the same memory page from which the Write command for the cycle N was received.
    An impulse write command 1R of the cycle N + 1 is written to the instruction register 29 during the maintenance time of the cycle N + 1. The decoder 30 identifies the transition command and excites the output bus of the Transition, while simultaneously stopping the excitation on the transition bus. As a result, a logic control circuit is energized — element 28, which allows the transition address containing the transition command to be input to the register 25 of the memory address. On the SAR write pulse of the N + 1 cycle, this transition address is written to the register (SAR) 25 during the T2 interval. Then the address of the transition is transmitted to the address circuits of the main memory 18 during the time interval-T8 on the memory selection pulse N + 1. However, at this point in time, a new setting of the state of the locking circuits 23 to 24 has occurred, and therefore the transition address is transferred to the address chains of the newly selected main memory page 18. Thus, not only does the memory page change, but, if desired, change Also, the byte address in this new page, both of which occur at the same time, namely, during this access to the memory in the time interval T8 of the N + 1 machine cycle, And the command that will be executed in the N + machine cycle 2 (not shown), selectable
    from the newly selected memory page in advance, during the N + 1 cycle.
    Consider another embodiment of the invention (Fig. 6) in which the operation of six blocks 44-49 can be programmed by entering the appropriate commands. Write to the command register 34. In this case, Write commands are used with two different opcodes. One of these operation codes denotes the Write to the first group command and, if it is detected in the decoder 35, the decoder signal is generated on the output bus of the SXL decoder. The second of these two. special operation codes denotes the Write command to the second group, and when it is detected in the decoder 35, a decoder signal is generated on the output bus of the SXH decoder. Blocks 44-49 are divided into two overlapping groups. The first group includes blocks 44-47, and the second - blocks 46-49. The output signal of the decoder corresponding to the SXL opcode is fed to the second inputs of AND 37-40 elements, to the last two elements AND 39 and 40 through the OR 43 element in block 36 to write to one or more blocks 44-47 of the first group, in accordance with with binary values written in bits, A, B, C and D commands. Similarly, the output of the decoder corresponding to the SHX operation code is fed to the second group of elements AND 39-42 (to the first two elements AND through the element OR 43) block 36 for recording in one or more blocks 46-49 of the second group, as before, in accordance with the binary values recorded in bits A, B, C and D of the command. The specific binary value that is written to any given block is determined by the binary value of in-specific one bit of the W, X, Y, Z command register to which the data input of this block is connected. Synchronization of the recording process in all these blocks is performed by a clock pulse T11, which is fed to all six elements I 37-42 via clock input 50.
    In this example, blocks 44 and 45 are used to select page 13 of the main memory. To do this, their outputs are connected to a decoder 51, from which four output page selection buses lead to a main memory subsystem, such as a main memory 18. Blocks 46 and 47 in this example are used to select a local memory page. For this, the outputs of these blocks are connected to the decoder 52, and four output page selection buses from the decoder 52 lead to addressable circuits of the local memory block. In this case, the volume of local memory will increase in four times the original. The initial volume may correspond to, for example, 32 independently addressable work registers, and such a group of 32 registers can be considered a page of local memory. In the example shown in Fig. 6, four such pages can be obtained, and the currently used page is determined by binary values in blocks 46 and 47. Such a post local memory structure allows different microprocessor operations to be allocated for various microprocessor operations. local memory pages, which ultimately leads to a decrease in the total information processing time. Blocks 48 and 49 (Fig. 6) are used to issue control signals for direct control 114 by one or more external devices that can be connected to or interconnected with a 1 "coprocessor. Blocks 48 and 49 can be used to control the selection of internal processor functions. In the example of FIG. 6, the Write command with operation code SXL is used to change the page of the main memory, or the local memory page, or both at the same time. The Write Operation Code SXH command is used to change the local memory page, or control signals to external devices, or both at the same time. This shows the flexibility and versatility of the proposed control device. The proposed control unit allows the microprocessor memory addressing range to be expanded compared to the addressing case by using the memory address in program instructions, i.e. the length of the address (the number of its binary bits) used in various instructions of the program containing the memory address field. With the help of such a device, the addressing range of the memory can be increased by 2.4.8 or 16 times with a minimum number of additional circuits and little effect on the microprocessor characteristics.
    ten

    F1 / G.2
    fug 5
    权利要求:
    Claims (5)
    [1]
    1. MANAGEMENT DEVICE IN THE DATA PROCESSING SYSTEM, containing a memory block, the output of which is connected to the information input of the command register, the control output of which is connected to the input of the command decoder, characterized in that, in order to obtain more flexibility in controlling the data processing system and make selective changes independent control parameters due to the contents of a single command, it contains a group of auxiliary control units and a load control unit, and the group of outputs of the decoder commands unified with the group of control inputs of the load control unit, the clock input of which is connected to the clock input of the device, the group of information inputs of the load control unit is connected to the group of address outputs of the command register, the first inputs of the auxiliary control unit groups are connected to the corresponding outputs of the command register data, the second inputs of the auxiliary units the group controls are connected to the corresponding outputs of the load control unit, the outputs of the auxiliary control unit groups are connected to the corresponding existing device outputs.
    [2]
    2. The device according to claim 1, characterized in that the load control unit contains a group of AND elements, the first inputs of which are connected to the corresponding inputs of the group of information inputs of the block, the second inputs of all elements and groups are connected to the corresponding inputs of the group of control inputs of the block, third inputs of all elements AND groups are connected to the clock input of the block, outputs of elements AND groups; connected to the corresponding outputs of the block.
    [3]
    3. The device according to claim 1, characterized in that the load control unit comprises an OR element and an AND group, the first inputs of the AND elements being connected. with the corresponding inputs of the group of information inputs of the block, the second inputs of the first and second elements of the AND group are connected to the first half of the inputs of the group of control inputs of the block and with the first input of the OR element, the output of which is connected to the second inputs of the third and fourth elements of the And group, the second inputs of the fifth and sixth elements AND groups are connected to the second half of the inputs of the group of control inputs of the block and to the second input of the OR element, the outputs of elements AND groups are connected to the corresponding outputs of the block.
    [4]
    4. The device according to claim 1, characterized in that the auxiliary control unit contains two elements NOT, two elements NOT, and the first input of the first element NOT connected to the first input of the block, the second input of which is connected to the first input of the second element NOT -And through the first element NOT - with the second input of the first element NOT-AND, the outputs of the first and second elements NOT-AND are connected through the second element NOT with the output of the block and with the second input of the second ~ · second element NOT-AND.
    [5]
    5. The device according to claim 1, characterized in that the auxiliary control unit comprises an element NOT, two AND elements and a trigger, the first input of the first AND element being connected to the first input of the block and through the NOT element to the first input of the second AND element, the second input which is connected to the second inputs of the block and the first element And, the output of which is connected to the input of the installation of the trigger, the reset input of which is connected to the output of the second element And, the output of the trigger is connected to the output of the block.
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    同族专利:
    公开号 | 公开日
    DE2962433D1|1982-05-19|
    AU4679379A|1980-01-03|
    IT7923793D0|1979-06-22|
    EP0006478B1|1982-04-07|
    JPS554695A|1980-01-14|
    US4179738A|1979-12-18|
    ES481636A1|1980-01-16|
    IT1162548B|1987-04-01|
    BR7903716A|1980-02-05|
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    CA1115849A|1982-01-05|
    EP0006478A1|1980-01-09|
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    申请号 | 申请日 | 专利标题
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